A prior art TTL tristate output device with reduced output capacitance is described in the Ferris U.S. Pat. No. 4,311,927 issued Jan. 19, 1982, entitled "Transistor Logic Tristate Device with Reduced Output Capacitance" with a related improvement described in the Ferris, et al. U.S. patent application Ser. No. 586,671 filed Mar. 6, 1984. The latter tristate output device 10, illustrated in FIG. 1, is provided with an input 12 for receiving binary data signals Vi of high and low potential and for transmitting output signals Vo to a common bus, not shown, coupled at the tristate device output 14. For operation in the bistate mode, the tristate device includes a pull-up transistor element comprising Darlington transistor pair Q2 and Q3 for sourcing current to the output 14 from high potential source Vcc and a pull-down transistor element Q4 for sinking current from the output 14 to low potential or ground. Phase splitter transistor element Q1 with collector resistor R1 is coupled at the input 12 to control the states of the pull-up and pull-down transistor elements in response to data signals Vi at the input. The pull-down transistor element Q4 includes a conventional squaring network at its base comprised of transistor Q5 with base and collector resistors R3 and R4.
For the tristate mode of operation, a prior art enable gate 20 illustrated in FIG. 2, is operatively coupled at the enable input 15 of tristate device 10. The high impedance third state is established at the output 14 of the tristate device when the enable gate output signal E is at low potential and the pull-up and phase splitter transistor elements are deprived of base drive current through diodes D1 and D2. For reducing the effective output capacitance during the high impedance third state, an active discharge sequence consisting of transistors Q7 and Q6 and diode cluster D3, D4, and D5 is operatively coupled between the base of pull-down transistor element Q4 and the enable input 15. The active discharge sequence affords a low impedance route to ground from the base of the pull-down element through transistor Q7 when the enable gate maintains a low potential enable signal E at enable input 15 and the tristate device is in the high impedance third state. As a result, low to high potential transitions on a common bus coupled at the tristate output 14 will not incidentally drive the pull-down transistor element Q4 to conduction. Any capacitive Miller feedback current through the collector to base capacitance of transistor Q4 is rapidly diverted and discharged to ground through active discharge transistor element Q7. During the bistate mode of operation when the enable signal E is at high potential, the active discharge sequence blocks current flow from high potential to the pull-down transistor element Q4.
The active discharge sequence as described in U.S. Pat. No. 4,311,927 comprises a sequence of three active element transistors in a double inversion series coupling between the enable gate and the base of the pull-down transistor. As a result of the double inversion, the collector potential of the active discharge transistor coupled at the base of the pull-down transistor element follows in phase the high or low potential of the enable signal E, discharging the base of the pull-down transistor when the enable signal E is at low potential and the tristate device 10 is in the high impedance third state. In the circuit of FIG. 1, one of the transistors in the active discharge sequence next to the enable input 15 is replaced with the passive diode cluster D3, D4, D5, coupled in a delta configuration and power supply resistors R5, R6, R7 coupled in a Y network. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor Q6 thereby depriving the active discharge transistor Q7 of base drive current when the enable signal E at the enable input 15 is at high potential for operation of the tristate device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor Q6 when the enable signal E is at low potential so that active discharge transistor Q7 actively conducts away from the base of the pull-down transistor Q4 for operation of the device with reduced output capacitance during the high impedance third state.
In either case there is double inversion. The collector potential of transistor Q6 follows out of phase with the enable signal potential E, and the collector potential of active discharge transistor Q7 follows in phase requiring two inversions of the enable signal E. The silicon area taken up by the active discharge sequence in either of the prior art tristate devices with low output capacitance is relatively large and this large area is multiplied when many tristate devices are tied to a common bus. Furthermore, either tristate device consumes power during bistate operation of the output device.
The prior art enable gate 20 shown in FIG. 2 is a bistate device with generates the enable signal E at enable gate output 16 from an enable gate input signal E at the enable gate input 18. The enable gate includes the enable pull-up Darlington transistor element Q22 and Q23, enable pull-down transistor element Q24, enable phase splitter transistor element 21 and collector resistor R21 operatively coupled to control the states of the enable pull-up and pull-down transistor elements, and a first enable input transistor element Q28 with collector resistor R28 and input diodes D21 and D22 operatively coupled for following and applying the enable gate signal input E to the base of the enable phase splitter transistor element 21. Because the collector potential of the active discharge transistor Q7 must follow in phase the enable gate output signal E with intermediate elements to block current flow from high potential during bistate operation, the double inversion sequence is required in the tristate device 10.
A prior art TTL internal buffer circuit for generating complementary data signals such as true and false data signals D and D from an input data signal D is illustrated in FIG. 3. The internal buffer circuit 30 is a bistate device with pull-up Darlington transistor element Q32 and Q33, pull-down transistor element Q34 and dual phase splitters Q31 and Q31a for controlling the state of the pull-up and pull-down transistor elements to provide high and low level output data signals D at the buffer output 36 in response to input data signals D at the buffer input 38. Input transistor element Q38 with collector resistor R38 and input diodes D31 and D32 are operatively coupled to apply an input data signal D to the bases of the dual phase splitter transistors Q31 and Q31a. Dual phase splitter transistor Q31a. is added to generate the complementary data signal and the collector potential of Q31a is tapped to provide the complementary input signal D to complementary buffer 40, a similar bistate buffer device which inverts the complementary input D to the complementary output data signal D. The collector potential of dual phase splitter Q31a may be used to provide the input to multiple complementary buffers such as buffer 40 although only one is shown by way of example in FIG. 3.
A schematic block diagram of this conventional buffer circuit for generating true and false data signals is illustrated in FIG. 4. The TTL bistate buffer 30 is inherently inverting at the output 36. The dual phase splitter Q31a is also inherently inverting at its collector 31a which is tapped to provide the complementary inputs D to one or more complementary buffers 40 which also inherently invert the complementary inputs at outputs 46 to provide the complementary output signals D. The complementary buffers 30 and 40 therefore provide the complementary true and false signals D and D from the single input signal D. A disadvantage of this arrangement using dual phase splitters however, is the problem of current hogging. The current mirror configuration of the dual phase splitters requires that the emitter currents equalize and a greater collector to emitter current in one phase splitter results in "hogging" of the base drive leaving insufficient current in the other, for example to drive multiple complementary buffers.